In a conventional data processing system, the functions of the main memory and the processor for processing data read out of the memory are clearly separated. In addition, in a large scale data processing system which needs a relatively large memory capacity, the main memory and the processor are, in many cases, physically separated.
In such data processing systems, a definite convention relating to the transfer of data is predetermined between the processor and the main memory, and the processor accesses the main memory for data in accordance with that convention. A unit which directly shares the access control to the main memory is called a memory controlling apparatus, and a memory controlling apparatus portion in the processor is herein called a memory controlling unit or storage controlling unit (SCU). The convention relating to the data transfer between the SCU and the main memory is called an interface.
In one of the prior art interface techniques, information concerning the type of access and a start pulse are sent from the SCU to the main memory, and the main memory, when it receives them, sends back a completion signal to the SCU after it has completed the requested operation. When the SCU receives the completion signal, it reads in the data or proceeds to the next process.
In this system, since the processor proceeds to the next process after it has received the completion signal from the main memory, a physical distance between the main memory and the processor does not affect the operation. Accordingly, even if the access time to the main memory as viewed from the SCU changes as a result of an increase of the memory capacity of the main memory or the reconfiguration of the main memory, the logic circuit need not be modified. The main memory can be used with various processors so long as the interface is common. However, because of loss of synchronization in the transfer of the start signal and the completion signal between the SCU and the main memory, the effective access time to the main memory as viewed from the SCU increases. In addition, since the transfer of information must be managed in the SCU and the main memory, the logical scale of the entire data processing system increases.
In order to avoid the above difficulties, in another prior art interface technique between the main memory and the SCU, the SCU carries out time control for the access to the main memory. In this system, after the SCU has sent the start signal to the main memory, it watches for an elapsed time which is determined in accordance with the type of access. For example, for a read operation, the SCU counts an elapsed time from the start signal, and after a predetermined time has elapsed the SCU instructs the main memory to send out the data to a data bus and the SCU loads the data on the data bus to a data register.
Since the SCU carries out the time control from the start of access to the main memory to the completion of the access, the time loss and the increase of the logic circuits concerning the data exchange are reduced as compared with the first-mentioned prior art system.
However, although this system resolves the difficulties encountered in the first-mentioned prior art system, it cancels out the advantage of the prior art system. In this system, the time system for the signal transfer in the interface between the processor and the main memory connected thereto is fixed for a given physical configuration, circuit configuration and control system, and hence the flexibility in effecting a change of the time system is lost. Consequently, this system is disadvantageous when the memory capacity of the main memory is increased, the memory configuration is changed, the access time is changed due to the development of faster memory cells, or the main memory is connected to a different processor.